LiteX demo¶
This example design features a LiteX+<CPU variant>-based SoC. It also includes DDR controller. First, enter this example’s directory:
cd litex_demo
Install the litex dependencies with the following:
pip install -r requirements.txt
There are multiple CPU types supported, choose one from the below commands to generate the design and build it.
Picorv32
./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_35 --variant a7-35 --build
./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=picorv32 --sys-clk-freq 80e6 --output-dir build/picorv32/arty_100 --variant a7-100 --build
VexRiscv
./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 --variant a7-35 --build
./src/litex/litex/boards/targets/arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_100 --variant a7-100 --build
Depending on which board and CPU-type you selected, the bitstream is loacted in:
cd build/<cpu-type>/<board>/gateware
Now you can upload the design with:
openFPGALoader -b arty_a7_100t top.bit
Note
This example uses baud rate of 115200 by default.
You should observe the following line in the OpenOCD output
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)
In the picocom terminal, you should observe the following output:
