sphinx-verilog-domain

Table Of Contents

Verilog Domain test

• verilog:port
• verilog:parameter
• verilog:module
  • ANSI style
  • Non-ANSI style
  • Module parameters
• Nesting and refs
• Cross-document refs
• verilog:namespace{,-push,-pop}
• Symbolator compatibility test
• Verilog Diagrams compatibility test

---

module d(cos_z0, sin_z0, done, z0, start, clock, reset);

Sine and cosine computer. Source

This module computes the sine and cosine of an input angle. The floating point numbers are represented as integers by scaling them up with a factor corresponding to the number of bits after the point.

output signed [19:0] cos_z0;

reg signed [19:0] cos_z0;

cosine of the input angle

output signed [19:0] sin_z0;

reg signed [19:0] sin_z0;

sine of the input angle

output done;

reg done;

output flag indicated completion of the computation

input signed [19:0] z0;

input angle

input start;

input that starts the computation on a posedge

input clock;

clock input

input reset;

reset input

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verilog:port