verilog:port¶
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input [0:1]
port_name_01;¶
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input
port_name_02[0:1];¶
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input [0:1]
port_name_03[0:1];¶
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input [0:1]
port_name_04[0:1],other_name_04;¶
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input [0:1]
other_name_05,port_name_05[0:1];¶
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input [0:1]
port_name_06[0:1],other_name_06[0:1];¶
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input [0:1]
port_name_07[0:1],other_name_07[0:1];¶
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input [0 : 1]
port_name_08[0 : 1],other_name_08[0 : 1];¶
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input [CONST/(2 * a)]
port_name_12;¶
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input
port_name_13[CONST/(2 * a)];¶
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input [CONST/(2 * a)]
port_name_14[CONST/(2 * a)];¶
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input [CONST/(2 * a)]
port_name_15[CONST/(2 * a)],other_name_15;¶
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input [CONST/(2 * a)]
other_name_16,port_name_16[CONST/(2 * a)];¶
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input [CONST/(2 * a)]
port_name_17[CONST/(2 * a)],other_name_17[CONST/(2 * a)];¶
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input [CONST/(2*a)]
port_name_18[CONST/(2*a)],other_name_18[CONST/(2*a)];¶
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input [CONST /(2 * a)]
port_name_19[CONST /(2 * a)],other_name_19[CONST /(2 * a)];¶
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input []
port_name_23;¶
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input
port_name_24[];¶
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input []
port_name_25[];¶
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input []
port_name_26[],other_name_26;¶
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input []
other_name_27,port_name_27[];¶
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input []
port_name_28[],other_name_28[];¶
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input []
port_name_29[],other_name_29[];¶
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input []
port_name_30[],other_name_30[];¶
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input [0:1][2:3]
port_name_34;¶
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input
port_name_35[0:1][2:3];¶
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input [0:1][2:3]
port_name_36[0:1][2:3];¶
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input [0:1][2:3]
port_name_37[0:1][2:3],other_name_37;¶
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input [0:1][2:3]
other_name_38,port_name_38[0:1][2:3];¶
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input [0:1][2:3]
port_name_39[0:1][2:3],other_name_39[0:1][2:3];¶
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input [0:1][2:3]
port_name_40[0:1][2:3],other_name_40[0:1][2:3];¶
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input [0 : 1][2 : 3]
port_name_41[0 : 1][2 : 3],other_name_41[0 : 1][2 : 3];¶
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input [0][CONST/(2 * a) : 4]
port_name_45;¶
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input
port_name_46[0][CONST/(2 * a) : 4];¶
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input [0][CONST/(2 * a) : 4]
port_name_47[0][CONST/(2 * a) : 4];¶
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input [0][CONST/(2 * a) : 4]
port_name_48[0][CONST/(2 * a) : 4],other_name_48;¶
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input [0][CONST/(2 * a) : 4]
other_name_49,port_name_49[0][CONST/(2 * a) : 4];¶
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input [0][CONST/(2 * a) : 4]
port_name_50[0][CONST/(2 * a) : 4],other_name_50[0][CONST/(2 * a) : 4];¶
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input [0][CONST/(2*a) :4]
port_name_51[0][CONST/(2*a) :4],other_name_51[0][CONST/(2*a) :4];¶
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input [0][CONST /(2 * a) : 4]
port_name_52[0][CONST /(2 * a) : 4],other_name_52[0][CONST /(2 * a) : 4];¶
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input [0][CONST/(2 * a)][]
port_name_56;¶
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input
port_name_57[0][CONST/(2 * a)][];¶
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input [0][CONST/(2 * a)][]
port_name_58[0][CONST/(2 * a)][];¶
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input [0][CONST/(2 * a)][]
port_name_59[0][CONST/(2 * a)][],other_name_59;¶
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input [0][CONST/(2 * a)][]
other_name_60,port_name_60[0][CONST/(2 * a)][];¶
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input [0][CONST/(2 * a)][]
port_name_61[0][CONST/(2 * a)][],other_name_61[0][CONST/(2 * a)][];¶
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input [0][CONST/(2*a)][]
port_name_62[0][CONST/(2*a)][],other_name_62[0][CONST/(2*a)][];¶
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input [0][CONST /(2 * a)][]
port_name_63[0][CONST /(2 * a)][],other_name_63[0][CONST /(2 * a)][];¶
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(* $flowmap_level = 1 * 2, attr = 4 *) input wire [DATA_WIDTH - 1:0]
a1,b1,c1;¶
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(* $flowmap_level=1 *) input
a2;¶
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(* $flowmap_level=1 *) input
\esc{aped[]tok()en;¶
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inout
fbmimicbidir;¶
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inout
DDRCASB;¶
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inout [width_b-1:0]
q_b;¶
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inout wire
PACKAGE_PIN;¶
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input
DataOut_i;¶
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input
clk,kld;¶
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input wire [31:0]
a3,b2;¶
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input
configupdate;¶
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input
dataa,datab,datac,datad;¶
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input
cam_enable;¶
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input
A1EN;¶
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input
clock,reset,req_0,req_1;¶
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input
B1EN;¶
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input [7:0]
tx_data;¶
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input [SIZE-1:0]
state;¶
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input
enable;¶
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input
in;¶
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input wire
I;¶
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input wire [7:0]
inp_b;¶
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input wire [WIDTH-1:0]
I;
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input wire
clk;
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input
Data0,Data1,Data2,Data3,Data4,Data5,Data6,Data7,Data8,Data9,Data10,Data11,Data12,Data13,Data14,Data15,Data16,Data17,Data18,Data19,Data20,Data21,Data22,Data23,Data24,Data25,Data26,Data27,Data28,Data29,Data30,Data31,Data32,Data33,Data34,Data35,Data36,Data37,Data38,Data39,Data40,Data41,Data42,Data43,Data44,Data45,Data46,Data47,Data48,Data49,Data50,Data51,Data52,Data53,Data54,Data55,Data56,Data57,Data58,Data59,Data60,Data61,Data62,Data63;¶
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input [width_clock-1:0]
clk;
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input
clock;
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input
clk;
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input
cl$k,\reset*;¶
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input
data,clk,reset;¶
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input
data_in;¶
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input
din_0,din_1,sel;¶
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input
enable;
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input integer
a,b;
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input
m_eth_payload_axis_tready;¶
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input reg [11:0]
zero2;¶
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input reg
zero1;¶
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input
req_3;¶
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input
reset;
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input signed
wire4;¶
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input signed [(B_WIDTH - 1) :0]
b;¶
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input wire
ci;¶
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input wire
S;¶
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input wire
D_OUT_0;¶
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input wire
S0,S1,S2,S3;¶
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input wire [(DataWidth - 1) :0]
wdata_a_i;¶
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input wire [6:0]
OPMODE;¶
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input wire [DATA_WIDTH/2-1:0]
b;
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input wire [NBITS-1:0]
I1;¶
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input wire
wrclk;¶
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output reg [31:0]
sum;¶
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output
CO;¶
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output
clk_out;¶
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output
rx_empty;¶
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output
y;¶
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output
clk_out;
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output
data_out_ack;¶
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output
out;¶
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output
parity_out;¶
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output reg
out;
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output
UUT_CO,UUT_ACCUMCO,UUT_SIGNEXTOUT;¶
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output [15:0]
decoder_out;¶
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output [3:0]
binary_out;¶
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output [7 : 0]
count;¶
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output [7:0]
count;
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output [7:0]
rx_data;¶
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output [WIDTHA+WIDTHB-1:0]
RES;¶
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output [Y_WIDTH-1:0]
X,Y,CO;¶
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output [number_of_channels-1:0]
dataout;¶
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output
gnt_0;¶
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output
q,\q~;¶
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output reg
fs_ce;¶
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output reg [WIDTH-1:0]
out;
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output reg
Q0,Q1,Q2,Q3;¶
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output reg [7:0]
x,y,z,w;¶
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output reg
carry_out,borrow_out,parity_out;¶
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output reg
wfi_insn_o;¶
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output reg [WIDTH-1:0]
POUT;¶
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output
sbox_decrypt_o;¶
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output signed [SIZEOUT-1:0]
REF_accum_out,accum_out;¶
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output wand
Y;
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output wand [3:0]
Y;
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output wire
CARRYCASCOUT;¶
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output wire
CIN;¶
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output wire [(DataWidth - 1) :0]
rdata_a_o;¶
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output wire [0:(PMPNumChan - 1)]
pmp_req_err_o;¶
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output wire [3:0]
CARRYOUT;¶
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output wire [DATA_WIDTH-1:0]
cout;¶
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output wire [NBITS-1:0]
O;¶
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output wire
wrclk;
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output wire [WIDTH-1:0]
POUT;
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output wor
X;
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output wor [3:0]
X;