Welcome to Topwrap!¶

Documentation

• Introduction to Topwrap
• Installing Topwrap
  • 1. Install required system packages
  • 2. Install the Topwrap user package
  • 3. Verify the installation
• Getting started
  • Design overview
  • Parsing Verilog files
  • Building designs with Topwrap
  • Command-line flow
• Advanced options
  • Creating block designs in the GUI
  • Command Line Interface (CLI)
• Sample projects
  • Embedded GUI
  • Constant
  • Inout
  • Hierarchy
  • PWM
  • HDMI
  • SoC
• Creating a design
  • Design description
  • IP description files
  • Interface description files
  • Resource path syntax
• Configuration
  • Configuration file location
  • Configuration precedence
  • Available config options
• Constructing, configuring and loading repositories
  • Using the open source IP cores library with Topwrap
• Interconnect generation
  • Format
  • Supported interconnect types
• Using FuseSoC for automation
  • Default tool for synthesis, bitstream generation and programming the FPGA
  • Additional build options
  • .core file template
  • Synthesis

Developer's Guide

• Setup
• Code style
  • Lint with nox
  • Lint with pre-commit
  • Tools
• Tests
  • Test execution
  • Test coverage
  • Updating kpm test data
• Wrapper
  • Wrapper
• IPWrapper class
  • IPWrapper
• IPConnect class
  • IPConnect
• ElaboratableWrapper class
  • ElaboratableWrapper
• Wrapper Port
  • WrapperPort
• FuseSocBuilder
  • FuseSocBuilder
• Interface Definition
  • InterfaceDefinition
  • get_interface_by_name
• Config
  • Config
  • ConfigManager
• Deducing interfaces
  • Step 1 - splitting ports into subsets
  • Step 2 - matching ports with interface signal names
  • Step 3 - inferring interface direction
  • Step 4 - computing interface matching score
• Validation of design
  • DataflowValidator
  • CheckResult
  • Tests for validation checks
• Examples
• Future planned enhancements in Topwrap
  • Library of open-source cores
  • Support for hierarchical block designs in Topwrap’s GUI
  • Support for parsing SystemVerilog sources
• Other possible improvements
  • Ability to produce top-level wrappers in VHDL
  • Bus management
  • Improve the process of recreating a design from a YAML file
  • Deeper integration with other tools
  • Provide a way to parse HDL sources from the GUI level
• Using KPM iframes inside docs
  • Usage
  • Tests
• Examples for Internal Representation
  • Simple
  • Interface
  • Hierarchical
  • Interconnect
  • Other
• IP-XACT format
  • General observations
  • Simple example
  • Interface example
  • Hierarchical example
  • Interconnect example
  • Other features
  • Conclusion