Target¶

Generate target¶

In order to generate a target containing AIG design run:

make target AIG_CONFIG=<path_to_aig_config> TARGET_CONFIG=<path_to_target_config>

Where the AIG_CONFIG is the path to the configuration for the AIG and the TARGET_CONFIG is the path to the target FPGA device configuration.

The generated target will be saved in aig_generated_target.py file.

To synthesize, place, route & generate bitstream, run:

python3 aig_generated_target.py --build

Expand the supported targets¶

If the chosen TARGET is not supported, one can easily extend the target generation with said target.

The first step is to extend the enums within aig_target.py with the new target:

class SoCTarget(StrEnum):
	arty = "digilent_arty"
	zvb = "antmicro_zynq_video_board"
	tg = "new_target"

class SoCPlatform(StrEnum):
	arty = "digilent_arty"
	zvb = "antmicro_zynq_video_board"
	tg = "platform_for_the_new_target"

class SoCCPU(StrEnum):
	vexriscv_smp = auto()
	zynq7000 = auto()
	new_cpu = auto() # If any

Then, in targets.py define the class representing the new target. This definition should contain the information about the bus standard and methods for registering interrupts and connecting memory buses.

class AIGTargetOnTARGET(AIGTarget): # 
	bus_standard = AIGBus.<wb/axil/axi> # 
	csr_bus = AIGBus.<wb/axil/axi>

	def __init__(self, frequency, size, config: Config): # 
		AIGTarget.__init__(self, SoCCPU.new_cpu, SoCPlatform.tg,
			SoCTarget.tg, size, frequency, config)

	def _add_interrupts(self, interupts: dict): # 
		irqs = []
		for no, irq in interupts.items():
			irqs.append(f'self.cpu.interrupt[{no}].eq({irq})')
		return [self._comb('[' + ',\n'.join(irqs) + ']')]

	def _connect_memory_bus(self, memoryBus: Bus): # 
		return f'self.add_master(master={memoryBus.soc_name})'