FuseSocBuilder¶

Topwrap supports generating FuseSoC .core files with FuseSocBuilder.The .core file contains information about source files and synthesis tools.

Generation of FuseSoC .core files is based on a Jinja template that defaults to topwrap/templates/core.yaml.j2, but can be overridden.

Here’s an example of how to generate a simple project:

from topwrap.fuse_helper import FuseSocBuilder
fuse = FuseSocBuilder()

# add source of the IPs used in the project
fuse.add_source('DMATop.v', 'verilogSource')

# add source of the top file
fuse.add_source('top.v', 'verilogSource')

# specify the names of the core file and the directory where sources are stored
# generate the project
fuse.build('build/top.core', 'sources')

class FuseSocBuilder(part)¶

Use this class to generate a FuseSoC .core file

add_dependency(dependency: str)¶

Adds a dependency to the list of dependencies in the core file

add_external_ip(vlnv: str, name: str)¶

Store information about IP Cores from Vivado library to generate hooks that will add the IPs in a TCL script.

add_source(filename, type)¶

Adds an HDL source to the list of sources in the core file

add_sources_dir(sources_dir: Collection[Path], core_path: Path)¶

Given a name of a directory, add all files found inside it. Recognize VHDL, Verilog, and XDC files.

build(top_name: str, core_path: Path, sources_dir: Collection[Path] = [], template_name: str | None = None)¶

Generate the final create .core file

Parameters:¶

sources_dir: Collection[Path] = []¶

additional directory with source files to add

template_name: str | None = None¶

name of jinja2 template to be used, either in working directory, or bundled with the package. defaults to a bundled template