Welcome to Topwrap!¶ Documentation Introduction to Topwrap Installing Topwrap 1. Install required system packages 2. Install the Topwrap user package 3. Verify the installation Getting started Design overview Adding Verilog sources to repository Building designs with Topwrap Command-line flow Advanced options Creating block designs in the GUI Sample projects Embedded GUI Constant Inout Hierarchy PWM HDMI SoC AXI interconnect Creating a design Design description IP description files Interface description files Resource path syntax Interface mapping and inference Interface mapping Interface inference Configuration Configuration file location Configuration precedence Available config options Constructing, configuring and loading repositories Supported resource types CLI Using the open source IP cores library with Topwrap Interconnect generation Format Supported interconnect types Using FuseSoC for automation Default tool for synthesis, bitstream generation and programming the FPGA Additional build options .core file template Synthesis Developer's Guide Setup Code style Lint with nox Lint with pre-commit Tools Tests Test execution Test coverage Updating kpm test data Internal Representation Class diagram Frontend & Backend Module Design Interface Interface mapping and inference Connections HDL Types Interconnects Miscellaneous A note on “sliced” vs. “independent” signals FuseSocBuilder FuseSocBuilder Interface Definition InterfaceDefinition get_interface_by_name Config Config ConfigManager Validation of design DataflowValidator CheckResult Tests for validation checks Future planned enhancements in Topwrap Library of open-source cores Support for hierarchical block designs in Topwrap’s GUI Support for parsing SystemVerilog sources Other possible improvements Ability to produce top-level wrappers in VHDL Bus management Improve the process of recreating a design from a YAML file Deeper integration with other tools Provide a way to parse HDL sources from the GUI level Using KPM iframes inside docs Usage Tests Examples for Internal Representation Simple Interface Hierarchical Interconnect Advanced SoC SoC_AXI Inverted Complex hierarchy parsing Other IP-XACT format General observations Simple example Interface example Hierarchical example Interconnect example Other features Conclusion Generator How to implement a Generator Lookup maps API Reference Interconnect INTERCONNECT_TYPES Repository API reference Parsed design examples Caliptra UART VeeR EL2 HMAC SHA256 SHA512 SHA3 Last update: 2026-05-07