WRITER¶

DMA DRAM writer.

Allows to fill DRAM with a predefined pattern using DMA.

Pattern¶

Provides access to RAM to store access pattern: mem_addr and mem_data. The pattern address space can be limited using the data_mask.

For example, having mem_adr filled with [ 0x04, 0x02, 0x03, … ] and mem_data filled with [ 0xff, 0xaa, 0x55, … ] and setting data_mask = 0b01, the pattern [(address, data), …] written will be: [(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), …] (wraps due to masking).

DRAM memory range that is being accessed can be configured using mem_mask.

To use this module, make sure that ready is 1, then write the desired number of transfers to count. Writing to the start CSR will initialize the operation. When the operation is ongoing ready will be 0.

Register Listing for WRITER¶

WRITER_START¶

Address: 0xf0002800 + 0x0 = 0xf0002800

Write to the register starts the transfer (if ready=1)

WRITER_READY¶

Address: 0xf0002800 + 0x4 = 0xf0002804

Indicates that the transfer is not ongoing

WRITER_MODULO¶

Address: 0xf0002800 + 0x8 = 0xf0002808

When set use modulo to calculate DMA transfers address rather than bit masking

WRITER_COUNT¶

Address: 0xf0002800 + 0xc = 0xf000280c

Desired number of DMA transfers

WRITER_DONE¶

Address: 0xf0002800 + 0x10 = 0xf0002810

Number of completed DMA transfers

WRITER_MEM_MASK¶

Address: 0xf0002800 + 0x14 = 0xf0002814

DRAM address mask for DMA transfers

WRITER_DATA_MASK¶

Address: 0xf0002800 + 0x18 = 0xf0002818

Pattern memory address mask

WRITER_DATA_DIV¶

Address: 0xf0002800 + 0x1c = 0xf000281c

Pattern memory address divisior-1

WRITER_INVERTER_DIVISOR_MASK¶

Address: 0xf0002800 + 0x20 = 0xf0002820

Divisor mask for selecting rows for which pattern data gets inverted

WRITER_INVERTER_SELECTION_MASK¶

Address: 0xf0002800 + 0x24 = 0xf0002824

Selection mask for selecting rows for which pattern data gets inverted

WRITER_LAST_ADDRESS¶

Address: 0xf0002800 + 0x28 = 0xf0002828

Number of completed DMA transfers