SDRAM¶

Register Listing for SDRAM¶

Register	Address
SDRAM_DFII_CONTROL	0xf0006000
SDRAM_DFII_PI0_COMMAND	0xf0006004
SDRAM_DFII_PI0_COMMAND_ISSUE	0xf0006008
SDRAM_DFII_PI0_ADDRESS	0xf000600c
SDRAM_DFII_PI0_BADDRESS	0xf0006010
SDRAM_DFII_PI0_WRDATA	0xf0006014
SDRAM_DFII_PI0_RDDATA	0xf0006018
SDRAM_DFII_PI1_COMMAND	0xf000601c
SDRAM_DFII_PI1_COMMAND_ISSUE	0xf0006020
SDRAM_DFII_PI1_ADDRESS	0xf0006024
SDRAM_DFII_PI1_BADDRESS	0xf0006028
SDRAM_DFII_PI1_WRDATA	0xf000602c
SDRAM_DFII_PI1_RDDATA	0xf0006030
SDRAM_DFII_PI2_COMMAND	0xf0006034
SDRAM_DFII_PI2_COMMAND_ISSUE	0xf0006038
SDRAM_DFII_PI2_ADDRESS	0xf000603c
SDRAM_DFII_PI2_BADDRESS	0xf0006040
SDRAM_DFII_PI2_WRDATA	0xf0006044
SDRAM_DFII_PI2_RDDATA	0xf0006048
SDRAM_DFII_PI3_COMMAND	0xf000604c
SDRAM_DFII_PI3_COMMAND_ISSUE	0xf0006050
SDRAM_DFII_PI3_ADDRESS	0xf0006054
SDRAM_DFII_PI3_BADDRESS	0xf0006058
SDRAM_DFII_PI3_WRDATA	0xf000605c
SDRAM_DFII_PI3_RDDATA	0xf0006060
SDRAM_DFII_PI4_COMMAND	0xf0006064
SDRAM_DFII_PI4_COMMAND_ISSUE	0xf0006068
SDRAM_DFII_PI4_ADDRESS	0xf000606c
SDRAM_DFII_PI4_BADDRESS	0xf0006070
SDRAM_DFII_PI4_WRDATA	0xf0006074
SDRAM_DFII_PI4_RDDATA	0xf0006078
SDRAM_DFII_PI5_COMMAND	0xf000607c
SDRAM_DFII_PI5_COMMAND_ISSUE	0xf0006080
SDRAM_DFII_PI5_ADDRESS	0xf0006084
SDRAM_DFII_PI5_BADDRESS	0xf0006088
SDRAM_DFII_PI5_WRDATA	0xf000608c
SDRAM_DFII_PI5_RDDATA	0xf0006090
SDRAM_DFII_PI6_COMMAND	0xf0006094
SDRAM_DFII_PI6_COMMAND_ISSUE	0xf0006098
SDRAM_DFII_PI6_ADDRESS	0xf000609c
SDRAM_DFII_PI6_BADDRESS	0xf00060a0
SDRAM_DFII_PI6_WRDATA	0xf00060a4
SDRAM_DFII_PI6_RDDATA	0xf00060a8
SDRAM_DFII_PI7_COMMAND	0xf00060ac
SDRAM_DFII_PI7_COMMAND_ISSUE	0xf00060b0
SDRAM_DFII_PI7_ADDRESS	0xf00060b4
SDRAM_DFII_PI7_BADDRESS	0xf00060b8
SDRAM_DFII_PI7_WRDATA	0xf00060bc
SDRAM_DFII_PI7_RDDATA	0xf00060c0
SDRAM_CONTROLLER_TRP	0xf00060c4
SDRAM_CONTROLLER_TRCD	0xf00060c8
SDRAM_CONTROLLER_TWR	0xf00060cc
SDRAM_CONTROLLER_TWTR	0xf00060d0
SDRAM_CONTROLLER_TREFI	0xf00060d4
SDRAM_CONTROLLER_TRFC	0xf00060d8
SDRAM_CONTROLLER_TFAW	0xf00060dc
SDRAM_CONTROLLER_TCCD	0xf00060e0
SDRAM_CONTROLLER_TCCD_WR	0xf00060e4
SDRAM_CONTROLLER_TRTP	0xf00060e8
SDRAM_CONTROLLER_TRRD	0xf00060ec
SDRAM_CONTROLLER_TRC	0xf00060f0
SDRAM_CONTROLLER_TRAS	0xf00060f4
SDRAM_CONTROLLER_LAST_ADDR_0	0xf00060f8
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0	0xf00060fc
SDRAM_CONTROLLER_LAST_ADDR_1	0xf0006100
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1	0xf0006104
SDRAM_CONTROLLER_LAST_ADDR_2	0xf0006108
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2	0xf000610c
SDRAM_CONTROLLER_LAST_ADDR_3	0xf0006110
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3	0xf0006114
SDRAM_CONTROLLER_LAST_ADDR_4	0xf0006118
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4	0xf000611c
SDRAM_CONTROLLER_LAST_ADDR_5	0xf0006120
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5	0xf0006124
SDRAM_CONTROLLER_LAST_ADDR_6	0xf0006128
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6	0xf000612c
SDRAM_CONTROLLER_LAST_ADDR_7	0xf0006130
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7	0xf0006134

SDRAM_DFII_CONTROL¶

Address: 0xf0006000 + 0x0 = 0xf0006000

Control DFI signals common to all phases

Field

Name

Description

[0]

SEL

Value	Description
`0b0`	Software (CPU) control.
`0b1`	Hardware control (default).

[1]

CKE

DFI clock enable bus

[2]

ODT

DFI on-die termination bus

[3]

RESET_N

DFI clock reset bus

SDRAM_DFII_PI0_COMMAND¶

Address: 0xf0006000 + 0x4 = 0xf0006004

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI0_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x8 = 0xf0006008

SDRAM_DFII_PI0_ADDRESS¶

Address: 0xf0006000 + 0xc = 0xf000600c

DFI address bus

SDRAM_DFII_PI0_BADDRESS¶

Address: 0xf0006000 + 0x10 = 0xf0006010

DFI bank address bus

SDRAM_DFII_PI0_WRDATA¶

Address: 0xf0006000 + 0x14 = 0xf0006014

DFI write data bus

SDRAM_DFII_PI0_RDDATA¶

Address: 0xf0006000 + 0x18 = 0xf0006018

DFI read data bus

SDRAM_DFII_PI1_COMMAND¶

Address: 0xf0006000 + 0x1c = 0xf000601c

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI1_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x20 = 0xf0006020

SDRAM_DFII_PI1_ADDRESS¶

Address: 0xf0006000 + 0x24 = 0xf0006024

DFI address bus

SDRAM_DFII_PI1_BADDRESS¶

Address: 0xf0006000 + 0x28 = 0xf0006028

DFI bank address bus

SDRAM_DFII_PI1_WRDATA¶

Address: 0xf0006000 + 0x2c = 0xf000602c

DFI write data bus

SDRAM_DFII_PI1_RDDATA¶

Address: 0xf0006000 + 0x30 = 0xf0006030

DFI read data bus

SDRAM_DFII_PI2_COMMAND¶

Address: 0xf0006000 + 0x34 = 0xf0006034

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI2_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x38 = 0xf0006038

SDRAM_DFII_PI2_ADDRESS¶

Address: 0xf0006000 + 0x3c = 0xf000603c

DFI address bus

SDRAM_DFII_PI2_BADDRESS¶

Address: 0xf0006000 + 0x40 = 0xf0006040

DFI bank address bus

SDRAM_DFII_PI2_WRDATA¶

Address: 0xf0006000 + 0x44 = 0xf0006044

DFI write data bus

SDRAM_DFII_PI2_RDDATA¶

Address: 0xf0006000 + 0x48 = 0xf0006048

DFI read data bus

SDRAM_DFII_PI3_COMMAND¶

Address: 0xf0006000 + 0x4c = 0xf000604c

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI3_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x50 = 0xf0006050

SDRAM_DFII_PI3_ADDRESS¶

Address: 0xf0006000 + 0x54 = 0xf0006054

DFI address bus

SDRAM_DFII_PI3_BADDRESS¶

Address: 0xf0006000 + 0x58 = 0xf0006058

DFI bank address bus

SDRAM_DFII_PI3_WRDATA¶

Address: 0xf0006000 + 0x5c = 0xf000605c

DFI write data bus

SDRAM_DFII_PI3_RDDATA¶

Address: 0xf0006000 + 0x60 = 0xf0006060

DFI read data bus

SDRAM_DFII_PI4_COMMAND¶

Address: 0xf0006000 + 0x64 = 0xf0006064

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI4_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x68 = 0xf0006068

SDRAM_DFII_PI4_ADDRESS¶

Address: 0xf0006000 + 0x6c = 0xf000606c

DFI address bus

SDRAM_DFII_PI4_BADDRESS¶

Address: 0xf0006000 + 0x70 = 0xf0006070

DFI bank address bus

SDRAM_DFII_PI4_WRDATA¶

Address: 0xf0006000 + 0x74 = 0xf0006074

DFI write data bus

SDRAM_DFII_PI4_RDDATA¶

Address: 0xf0006000 + 0x78 = 0xf0006078

DFI read data bus

SDRAM_DFII_PI5_COMMAND¶

Address: 0xf0006000 + 0x7c = 0xf000607c

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI5_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x80 = 0xf0006080

SDRAM_DFII_PI5_ADDRESS¶

Address: 0xf0006000 + 0x84 = 0xf0006084

DFI address bus

SDRAM_DFII_PI5_BADDRESS¶

Address: 0xf0006000 + 0x88 = 0xf0006088

DFI bank address bus

SDRAM_DFII_PI5_WRDATA¶

Address: 0xf0006000 + 0x8c = 0xf000608c

DFI write data bus

SDRAM_DFII_PI5_RDDATA¶

Address: 0xf0006000 + 0x90 = 0xf0006090

DFI read data bus

SDRAM_DFII_PI6_COMMAND¶

Address: 0xf0006000 + 0x94 = 0xf0006094

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI6_COMMAND_ISSUE¶

Address: 0xf0006000 + 0x98 = 0xf0006098

SDRAM_DFII_PI6_ADDRESS¶

Address: 0xf0006000 + 0x9c = 0xf000609c

DFI address bus

SDRAM_DFII_PI6_BADDRESS¶

Address: 0xf0006000 + 0xa0 = 0xf00060a0

DFI bank address bus

SDRAM_DFII_PI6_WRDATA¶

Address: 0xf0006000 + 0xa4 = 0xf00060a4

DFI write data bus

SDRAM_DFII_PI6_RDDATA¶

Address: 0xf0006000 + 0xa8 = 0xf00060a8

DFI read data bus

SDRAM_DFII_PI7_COMMAND¶

Address: 0xf0006000 + 0xac = 0xf00060ac

Control DFI signals on a single phase

Field	Name	Description
[0]	CS	DFI chip select bus
[1]	WE	DFI write enable bus
[2]	CAS	DFI column address strobe bus
[3]	RAS	DFI row address strobe bus
[4]	WREN	DFI write data enable bus
[5]	RDEN	DFI read data enable bus

SDRAM_DFII_PI7_COMMAND_ISSUE¶

Address: 0xf0006000 + 0xb0 = 0xf00060b0

SDRAM_DFII_PI7_ADDRESS¶

Address: 0xf0006000 + 0xb4 = 0xf00060b4

DFI address bus

SDRAM_DFII_PI7_BADDRESS¶

Address: 0xf0006000 + 0xb8 = 0xf00060b8

DFI bank address bus

SDRAM_DFII_PI7_WRDATA¶

Address: 0xf0006000 + 0xbc = 0xf00060bc

DFI write data bus

SDRAM_DFII_PI7_RDDATA¶

Address: 0xf0006000 + 0xc0 = 0xf00060c0

DFI read data bus

SDRAM_CONTROLLER_TRP¶

Address: 0xf0006000 + 0xc4 = 0xf00060c4

SDRAM_CONTROLLER_TRCD¶

Address: 0xf0006000 + 0xc8 = 0xf00060c8

SDRAM_CONTROLLER_TWR¶

Address: 0xf0006000 + 0xcc = 0xf00060cc

SDRAM_CONTROLLER_TWTR¶

Address: 0xf0006000 + 0xd0 = 0xf00060d0

SDRAM_CONTROLLER_TREFI¶

Address: 0xf0006000 + 0xd4 = 0xf00060d4

SDRAM_CONTROLLER_TRFC¶

Address: 0xf0006000 + 0xd8 = 0xf00060d8

SDRAM_CONTROLLER_TFAW¶

Address: 0xf0006000 + 0xdc = 0xf00060dc

SDRAM_CONTROLLER_TCCD¶

Address: 0xf0006000 + 0xe0 = 0xf00060e0

SDRAM_CONTROLLER_TCCD_WR¶

Address: 0xf0006000 + 0xe4 = 0xf00060e4

SDRAM_CONTROLLER_TRTP¶

Address: 0xf0006000 + 0xe8 = 0xf00060e8

SDRAM_CONTROLLER_TRRD¶

Address: 0xf0006000 + 0xec = 0xf00060ec

SDRAM_CONTROLLER_TRC¶

Address: 0xf0006000 + 0xf0 = 0xf00060f0

SDRAM_CONTROLLER_TRAS¶

Address: 0xf0006000 + 0xf4 = 0xf00060f4

SDRAM_CONTROLLER_LAST_ADDR_0¶

Address: 0xf0006000 + 0xf8 = 0xf00060f8

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0¶

Address: 0xf0006000 + 0xfc = 0xf00060fc

SDRAM_CONTROLLER_LAST_ADDR_1¶

Address: 0xf0006000 + 0x100 = 0xf0006100

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1¶

Address: 0xf0006000 + 0x104 = 0xf0006104

SDRAM_CONTROLLER_LAST_ADDR_2¶

Address: 0xf0006000 + 0x108 = 0xf0006108

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2¶

Address: 0xf0006000 + 0x10c = 0xf000610c

SDRAM_CONTROLLER_LAST_ADDR_3¶

Address: 0xf0006000 + 0x110 = 0xf0006110

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3¶

Address: 0xf0006000 + 0x114 = 0xf0006114

SDRAM_CONTROLLER_LAST_ADDR_4¶

Address: 0xf0006000 + 0x118 = 0xf0006118

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4¶

Address: 0xf0006000 + 0x11c = 0xf000611c

SDRAM_CONTROLLER_LAST_ADDR_5¶

Address: 0xf0006000 + 0x120 = 0xf0006120

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5¶

Address: 0xf0006000 + 0x124 = 0xf0006124

SDRAM_CONTROLLER_LAST_ADDR_6¶

Address: 0xf0006000 + 0x128 = 0xf0006128

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6¶

Address: 0xf0006000 + 0x12c = 0xf000612c

SDRAM_CONTROLLER_LAST_ADDR_7¶

Address: 0xf0006000 + 0x130 = 0xf0006130

SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7¶

Address: 0xf0006000 + 0x134 = 0xf0006134

Last update: 2024-12-18