READER

DMA DRAM reader.

Allows to check DRAM contents against a predefined pattern using DMA.

Pattern

Provides access to RAM to store access pattern: mem_addr and mem_data. The pattern address space can be limited using the data_mask.

For example, having mem_adr filled with [ 0x04, 0x02, 0x03, … ] and mem_data filled with [ 0xff, 0xaa, 0x55, … ] and setting data_mask = 0b01, the pattern [(address, data), …] written will be: [(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), …] (wraps due to masking).

DRAM memory range that is being accessed can be configured using mem_mask.

To use this module, make sure that ready is 1, then write the desired number of transfers to count. Writing to the start CSR will initialize the operation. When the operation is ongoing ready will be 0.

Reading errors

This module allows to check the locations of errors in the memory. It scans the configured memory area and compares the values read to the predefined pattern. If skip_fifo is 0, this module will stop after each error encountered, so that it can be examined. Wait until the error_ready CSR is 1. Then use the CSRs error_offset, error_data and error_expected to examine the errors in the current transfer. To continue reading, write 1 to error_continue CSR. Setting skip_fifo to 1 will disable this behaviour entirely.

The final number of errors can be read from error_count. NOTE: This value represents the number of erroneous DMA transfers.

The current progress can be read from the done CSR.

Register Listing for READER

Register

Address

READER_START

0xf0003000

READER_READY

0xf0003004

READER_MODULO

0xf0003008

READER_COUNT

0xf000300c

READER_DONE

0xf0003010

READER_MEM_MASK

0xf0003014

READER_DATA_MASK

0xf0003018

READER_DATA_DIV

0xf000301c

READER_INVERTER_DIVISOR_MASK

0xf0003020

READER_INVERTER_SELECTION_MASK

0xf0003024

READER_ERROR_COUNT

0xf0003028

READER_SKIP_FIFO

0xf000302c

READER_ERROR_OFFSET

0xf0003030

READER_ERROR_DATA15

0xf0003034

READER_ERROR_DATA14

0xf0003038

READER_ERROR_DATA13

0xf000303c

READER_ERROR_DATA12

0xf0003040

READER_ERROR_DATA11

0xf0003044

READER_ERROR_DATA10

0xf0003048

READER_ERROR_DATA9

0xf000304c

READER_ERROR_DATA8

0xf0003050

READER_ERROR_DATA7

0xf0003054

READER_ERROR_DATA6

0xf0003058

READER_ERROR_DATA5

0xf000305c

READER_ERROR_DATA4

0xf0003060

READER_ERROR_DATA3

0xf0003064

READER_ERROR_DATA2

0xf0003068

READER_ERROR_DATA1

0xf000306c

READER_ERROR_DATA0

0xf0003070

READER_ERROR_EXPECTED15

0xf0003074

READER_ERROR_EXPECTED14

0xf0003078

READER_ERROR_EXPECTED13

0xf000307c

READER_ERROR_EXPECTED12

0xf0003080

READER_ERROR_EXPECTED11

0xf0003084

READER_ERROR_EXPECTED10

0xf0003088

READER_ERROR_EXPECTED9

0xf000308c

READER_ERROR_EXPECTED8

0xf0003090

READER_ERROR_EXPECTED7

0xf0003094

READER_ERROR_EXPECTED6

0xf0003098

READER_ERROR_EXPECTED5

0xf000309c

READER_ERROR_EXPECTED4

0xf00030a0

READER_ERROR_EXPECTED3

0xf00030a4

READER_ERROR_EXPECTED2

0xf00030a8

READER_ERROR_EXPECTED1

0xf00030ac

READER_ERROR_EXPECTED0

0xf00030b0

READER_ERROR_READY

0xf00030b4

READER_ERROR_CONTINUE

0xf00030b8

READER_START

Address: 0xf0003000 + 0x0 = 0xf0003000

Write to the register starts the transfer (if ready=1)

READER_READY

Address: 0xf0003000 + 0x4 = 0xf0003004

Indicates that the transfer is not ongoing

READER_MODULO

Address: 0xf0003000 + 0x8 = 0xf0003008

When set use modulo to calculate DMA transfers address rather than bit masking

READER_COUNT

Address: 0xf0003000 + 0xc = 0xf000300c

Desired number of DMA transfers

READER_DONE

Address: 0xf0003000 + 0x10 = 0xf0003010

Number of completed DMA transfers

READER_MEM_MASK

Address: 0xf0003000 + 0x14 = 0xf0003014

DRAM address mask for DMA transfers

READER_DATA_MASK

Address: 0xf0003000 + 0x18 = 0xf0003018

Pattern memory address mask

READER_DATA_DIV

Address: 0xf0003000 + 0x1c = 0xf000301c

Pattern memory address divisior-1

READER_INVERTER_DIVISOR_MASK

Address: 0xf0003000 + 0x20 = 0xf0003020

Divisor mask for selecting rows for which pattern data gets inverted

READER_INVERTER_SELECTION_MASK

Address: 0xf0003000 + 0x24 = 0xf0003024

Selection mask for selecting rows for which pattern data gets inverted

READER_ERROR_COUNT

Address: 0xf0003000 + 0x28 = 0xf0003028

Number of errors detected

READER_SKIP_FIFO

Address: 0xf0003000 + 0x2c = 0xf000302c

Skip waiting for user to read the errors FIFO

READER_ERROR_OFFSET

Address: 0xf0003000 + 0x30 = 0xf0003030

Current offset of the error

READER_ERROR_DATA15

Address: 0xf0003000 + 0x34 = 0xf0003034

Bits 480-511 of READER_ERROR_DATA. Erroneous value read from DRAM memory

READER_ERROR_DATA14

Address: 0xf0003000 + 0x38 = 0xf0003038

Bits 448-479 of READER_ERROR_DATA.

READER_ERROR_DATA13

Address: 0xf0003000 + 0x3c = 0xf000303c

Bits 416-447 of READER_ERROR_DATA.

READER_ERROR_DATA12

Address: 0xf0003000 + 0x40 = 0xf0003040

Bits 384-415 of READER_ERROR_DATA.

READER_ERROR_DATA11

Address: 0xf0003000 + 0x44 = 0xf0003044

Bits 352-383 of READER_ERROR_DATA.

READER_ERROR_DATA10

Address: 0xf0003000 + 0x48 = 0xf0003048

Bits 320-351 of READER_ERROR_DATA.

READER_ERROR_DATA9

Address: 0xf0003000 + 0x4c = 0xf000304c

Bits 288-319 of READER_ERROR_DATA.

READER_ERROR_DATA8

Address: 0xf0003000 + 0x50 = 0xf0003050

Bits 256-287 of READER_ERROR_DATA.

READER_ERROR_DATA7

Address: 0xf0003000 + 0x54 = 0xf0003054

Bits 224-255 of READER_ERROR_DATA.

READER_ERROR_DATA6

Address: 0xf0003000 + 0x58 = 0xf0003058

Bits 192-223 of READER_ERROR_DATA.

READER_ERROR_DATA5

Address: 0xf0003000 + 0x5c = 0xf000305c

Bits 160-191 of READER_ERROR_DATA.

READER_ERROR_DATA4

Address: 0xf0003000 + 0x60 = 0xf0003060

Bits 128-159 of READER_ERROR_DATA.

READER_ERROR_DATA3

Address: 0xf0003000 + 0x64 = 0xf0003064

Bits 96-127 of READER_ERROR_DATA.

READER_ERROR_DATA2

Address: 0xf0003000 + 0x68 = 0xf0003068

Bits 64-95 of READER_ERROR_DATA.

READER_ERROR_DATA1

Address: 0xf0003000 + 0x6c = 0xf000306c

Bits 32-63 of READER_ERROR_DATA.

READER_ERROR_DATA0

Address: 0xf0003000 + 0x70 = 0xf0003070

Bits 0-31 of READER_ERROR_DATA.

READER_ERROR_EXPECTED15

Address: 0xf0003000 + 0x74 = 0xf0003074

Bits 480-511 of READER_ERROR_EXPECTED. Value expected to be read from DRAM memory

READER_ERROR_EXPECTED14

Address: 0xf0003000 + 0x78 = 0xf0003078

Bits 448-479 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED13

Address: 0xf0003000 + 0x7c = 0xf000307c

Bits 416-447 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED12

Address: 0xf0003000 + 0x80 = 0xf0003080

Bits 384-415 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED11

Address: 0xf0003000 + 0x84 = 0xf0003084

Bits 352-383 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED10

Address: 0xf0003000 + 0x88 = 0xf0003088

Bits 320-351 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED9

Address: 0xf0003000 + 0x8c = 0xf000308c

Bits 288-319 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED8

Address: 0xf0003000 + 0x90 = 0xf0003090

Bits 256-287 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED7

Address: 0xf0003000 + 0x94 = 0xf0003094

Bits 224-255 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED6

Address: 0xf0003000 + 0x98 = 0xf0003098

Bits 192-223 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED5

Address: 0xf0003000 + 0x9c = 0xf000309c

Bits 160-191 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED4

Address: 0xf0003000 + 0xa0 = 0xf00030a0

Bits 128-159 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED3

Address: 0xf0003000 + 0xa4 = 0xf00030a4

Bits 96-127 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED2

Address: 0xf0003000 + 0xa8 = 0xf00030a8

Bits 64-95 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED1

Address: 0xf0003000 + 0xac = 0xf00030ac

Bits 32-63 of READER_ERROR_EXPECTED.

READER_ERROR_EXPECTED0

Address: 0xf0003000 + 0xb0 = 0xf00030b0

Bits 0-31 of READER_ERROR_EXPECTED.

READER_ERROR_READY

Address: 0xf0003000 + 0xb4 = 0xf00030b4

Error detected and ready to read

READER_ERROR_CONTINUE

Address: 0xf0003000 + 0xb8 = 0xf00030b8

Continue reading until the next error


Last update: 2024-11-07