SDRAM¶
Register Listing for SDRAM¶
Register |
Address |
---|---|
SDRAM_DFII_CONTROL¶
Address: 0xf0006800 + 0x0 = 0xf0006800
Control DFI signals common to all phases
Field |
Name |
Description |
||||||
---|---|---|---|---|---|---|---|---|
[0] |
SEL |
|
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[1] |
CKE |
DFI clock enable bus |
||||||
[2] |
ODT |
DFI on-die termination bus |
||||||
[3] |
RESET_N |
DFI clock reset bus |
SDRAM_DFII_PI0_COMMAND¶
Address: 0xf0006800 + 0x4 = 0xf0006804
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI0_COMMAND_ISSUE¶
Address: 0xf0006800 + 0x8 = 0xf0006808
SDRAM_DFII_PI0_ADDRESS¶
Address: 0xf0006800 + 0xc = 0xf000680c
DFI address bus
SDRAM_DFII_PI0_BADDRESS¶
Address: 0xf0006800 + 0x10 = 0xf0006810
DFI bank address bus
SDRAM_DFII_PI0_WRDATA1¶
Address: 0xf0006800 + 0x14 = 0xf0006814
Bits 32-63 of SDRAM_DFII_PI0_WRDATA. DFI write data bus
SDRAM_DFII_PI0_WRDATA0¶
Address: 0xf0006800 + 0x18 = 0xf0006818
Bits 0-31 of SDRAM_DFII_PI0_WRDATA.
SDRAM_DFII_PI0_RDDATA1¶
Address: 0xf0006800 + 0x1c = 0xf000681c
Bits 32-63 of SDRAM_DFII_PI0_RDDATA. DFI read data bus
SDRAM_DFII_PI0_RDDATA0¶
Address: 0xf0006800 + 0x20 = 0xf0006820
Bits 0-31 of SDRAM_DFII_PI0_RDDATA.
SDRAM_DFII_PI1_COMMAND¶
Address: 0xf0006800 + 0x24 = 0xf0006824
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI1_COMMAND_ISSUE¶
Address: 0xf0006800 + 0x28 = 0xf0006828
SDRAM_DFII_PI1_ADDRESS¶
Address: 0xf0006800 + 0x2c = 0xf000682c
DFI address bus
SDRAM_DFII_PI1_BADDRESS¶
Address: 0xf0006800 + 0x30 = 0xf0006830
DFI bank address bus
SDRAM_DFII_PI1_WRDATA1¶
Address: 0xf0006800 + 0x34 = 0xf0006834
Bits 32-63 of SDRAM_DFII_PI1_WRDATA. DFI write data bus
SDRAM_DFII_PI1_WRDATA0¶
Address: 0xf0006800 + 0x38 = 0xf0006838
Bits 0-31 of SDRAM_DFII_PI1_WRDATA.
SDRAM_DFII_PI1_RDDATA1¶
Address: 0xf0006800 + 0x3c = 0xf000683c
Bits 32-63 of SDRAM_DFII_PI1_RDDATA. DFI read data bus
SDRAM_DFII_PI1_RDDATA0¶
Address: 0xf0006800 + 0x40 = 0xf0006840
Bits 0-31 of SDRAM_DFII_PI1_RDDATA.
SDRAM_DFII_PI2_COMMAND¶
Address: 0xf0006800 + 0x44 = 0xf0006844
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI2_COMMAND_ISSUE¶
Address: 0xf0006800 + 0x48 = 0xf0006848
SDRAM_DFII_PI2_ADDRESS¶
Address: 0xf0006800 + 0x4c = 0xf000684c
DFI address bus
SDRAM_DFII_PI2_BADDRESS¶
Address: 0xf0006800 + 0x50 = 0xf0006850
DFI bank address bus
SDRAM_DFII_PI2_WRDATA1¶
Address: 0xf0006800 + 0x54 = 0xf0006854
Bits 32-63 of SDRAM_DFII_PI2_WRDATA. DFI write data bus
SDRAM_DFII_PI2_WRDATA0¶
Address: 0xf0006800 + 0x58 = 0xf0006858
Bits 0-31 of SDRAM_DFII_PI2_WRDATA.
SDRAM_DFII_PI2_RDDATA1¶
Address: 0xf0006800 + 0x5c = 0xf000685c
Bits 32-63 of SDRAM_DFII_PI2_RDDATA. DFI read data bus
SDRAM_DFII_PI2_RDDATA0¶
Address: 0xf0006800 + 0x60 = 0xf0006860
Bits 0-31 of SDRAM_DFII_PI2_RDDATA.
SDRAM_DFII_PI3_COMMAND¶
Address: 0xf0006800 + 0x64 = 0xf0006864
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI3_COMMAND_ISSUE¶
Address: 0xf0006800 + 0x68 = 0xf0006868
SDRAM_DFII_PI3_ADDRESS¶
Address: 0xf0006800 + 0x6c = 0xf000686c
DFI address bus
SDRAM_DFII_PI3_BADDRESS¶
Address: 0xf0006800 + 0x70 = 0xf0006870
DFI bank address bus
SDRAM_DFII_PI3_WRDATA1¶
Address: 0xf0006800 + 0x74 = 0xf0006874
Bits 32-63 of SDRAM_DFII_PI3_WRDATA. DFI write data bus
SDRAM_DFII_PI3_WRDATA0¶
Address: 0xf0006800 + 0x78 = 0xf0006878
Bits 0-31 of SDRAM_DFII_PI3_WRDATA.
SDRAM_DFII_PI3_RDDATA1¶
Address: 0xf0006800 + 0x7c = 0xf000687c
Bits 32-63 of SDRAM_DFII_PI3_RDDATA. DFI read data bus
SDRAM_DFII_PI3_RDDATA0¶
Address: 0xf0006800 + 0x80 = 0xf0006880
Bits 0-31 of SDRAM_DFII_PI3_RDDATA.
SDRAM_CONTROLLER_TRP¶
Address: 0xf0006800 + 0x84 = 0xf0006884
SDRAM_CONTROLLER_TRCD¶
Address: 0xf0006800 + 0x88 = 0xf0006888
SDRAM_CONTROLLER_TWR¶
Address: 0xf0006800 + 0x8c = 0xf000688c
SDRAM_CONTROLLER_TWTR¶
Address: 0xf0006800 + 0x90 = 0xf0006890
SDRAM_CONTROLLER_TREFI¶
Address: 0xf0006800 + 0x94 = 0xf0006894
SDRAM_CONTROLLER_TRFC¶
Address: 0xf0006800 + 0x98 = 0xf0006898
SDRAM_CONTROLLER_TFAW¶
Address: 0xf0006800 + 0x9c = 0xf000689c
SDRAM_CONTROLLER_TCCD¶
Address: 0xf0006800 + 0xa0 = 0xf00068a0
SDRAM_CONTROLLER_TCCD_WR¶
Address: 0xf0006800 + 0xa4 = 0xf00068a4
SDRAM_CONTROLLER_TRTP¶
Address: 0xf0006800 + 0xa8 = 0xf00068a8
SDRAM_CONTROLLER_TRRD¶
Address: 0xf0006800 + 0xac = 0xf00068ac
SDRAM_CONTROLLER_TRC¶
Address: 0xf0006800 + 0xb0 = 0xf00068b0
SDRAM_CONTROLLER_TRAS¶
Address: 0xf0006800 + 0xb4 = 0xf00068b4
SDRAM_CONTROLLER_TZQCS¶
Address: 0xf0006800 + 0xb8 = 0xf00068b8
SDRAM_CONTROLLER_LAST_ADDR_0¶
Address: 0xf0006800 + 0xbc = 0xf00068bc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0¶
Address: 0xf0006800 + 0xc0 = 0xf00068c0
SDRAM_CONTROLLER_LAST_ADDR_1¶
Address: 0xf0006800 + 0xc4 = 0xf00068c4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1¶
Address: 0xf0006800 + 0xc8 = 0xf00068c8
SDRAM_CONTROLLER_LAST_ADDR_2¶
Address: 0xf0006800 + 0xcc = 0xf00068cc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2¶
Address: 0xf0006800 + 0xd0 = 0xf00068d0
SDRAM_CONTROLLER_LAST_ADDR_3¶
Address: 0xf0006800 + 0xd4 = 0xf00068d4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3¶
Address: 0xf0006800 + 0xd8 = 0xf00068d8
SDRAM_CONTROLLER_LAST_ADDR_4¶
Address: 0xf0006800 + 0xdc = 0xf00068dc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4¶
Address: 0xf0006800 + 0xe0 = 0xf00068e0
SDRAM_CONTROLLER_LAST_ADDR_5¶
Address: 0xf0006800 + 0xe4 = 0xf00068e4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5¶
Address: 0xf0006800 + 0xe8 = 0xf00068e8
SDRAM_CONTROLLER_LAST_ADDR_6¶
Address: 0xf0006800 + 0xec = 0xf00068ec
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6¶
Address: 0xf0006800 + 0xf0 = 0xf00068f0
SDRAM_CONTROLLER_LAST_ADDR_7¶
Address: 0xf0006800 + 0xf4 = 0xf00068f4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7¶
Address: 0xf0006800 + 0xf8 = 0xf00068f8
SDRAM_CONTROLLER_LAST_ADDR_8¶
Address: 0xf0006800 + 0xfc = 0xf00068fc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_8¶
Address: 0xf0006800 + 0x100 = 0xf0006900
SDRAM_CONTROLLER_LAST_ADDR_9¶
Address: 0xf0006800 + 0x104 = 0xf0006904
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_9¶
Address: 0xf0006800 + 0x108 = 0xf0006908
SDRAM_CONTROLLER_LAST_ADDR_10¶
Address: 0xf0006800 + 0x10c = 0xf000690c
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_10¶
Address: 0xf0006800 + 0x110 = 0xf0006910
SDRAM_CONTROLLER_LAST_ADDR_11¶
Address: 0xf0006800 + 0x114 = 0xf0006914
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_11¶
Address: 0xf0006800 + 0x118 = 0xf0006918
SDRAM_CONTROLLER_LAST_ADDR_12¶
Address: 0xf0006800 + 0x11c = 0xf000691c
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_12¶
Address: 0xf0006800 + 0x120 = 0xf0006920
SDRAM_CONTROLLER_LAST_ADDR_13¶
Address: 0xf0006800 + 0x124 = 0xf0006924
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_13¶
Address: 0xf0006800 + 0x128 = 0xf0006928
SDRAM_CONTROLLER_LAST_ADDR_14¶
Address: 0xf0006800 + 0x12c = 0xf000692c
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_14¶
Address: 0xf0006800 + 0x130 = 0xf0006930
SDRAM_CONTROLLER_LAST_ADDR_15¶
Address: 0xf0006800 + 0x134 = 0xf0006934
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_15¶
Address: 0xf0006800 + 0x138 = 0xf0006938