READER¶
DMA DRAM reader.
Allows to check DRAM contents against a predefined pattern using DMA.
Pattern¶
Provides access to RAM to store access pattern: mem_addr and mem_data. The pattern address space can be limited using the data_mask.
For example, having mem_adr filled with [ 0x04, 0x02, 0x03, … ] and mem_data filled with [ 0xff, 0xaa, 0x55, … ] and setting data_mask = 0b01, the pattern [(address, data), …] written will be: [(0x04, 0xff), (0x02, 0xaa), (0x04, 0xff), …] (wraps due to masking).
DRAM memory range that is being accessed can be configured using mem_mask.
To use this module, make sure that ready is 1, then write the desired number of transfers to count. Writing to the start CSR will initialize the operation. When the operation is ongoing ready will be 0.
Reading errors¶
This module allows to check the locations of errors in the memory. It scans the configured memory area and compares the values read to the predefined pattern. If skip_fifo is 0, this module will stop after each error encountered, so that it can be examined. Wait until the error_ready CSR is 1. Then use the CSRs error_offset, error_data and error_expected to examine the errors in the current transfer. To continue reading, write 1 to error_continue CSR. Setting skip_fifo to 1 will disable this behavior entirely.
The final number of errors can be read from error_count. NOTE: This value represents the number of erroneous DMA transfers.
The current progress can be read from the done CSR.
Register Listing for READER¶
Register |
Address |
|---|---|
READER_START¶
Address: 0xf0003800 + 0x0 = 0xf0003800
Write to the register starts the transfer (if ready=1)
READER_READY¶
Address: 0xf0003800 + 0x4 = 0xf0003804
Indicates that the transfer is not ongoing
READER_MODULO¶
Address: 0xf0003800 + 0x8 = 0xf0003808
When set use modulo to calculate DMA transfers address rather than bit masking
READER_COUNT¶
Address: 0xf0003800 + 0xc = 0xf000380c
Desired number of DMA transfers
READER_DONE¶
Address: 0xf0003800 + 0x10 = 0xf0003810
Number of completed DMA transfers
READER_MEM_MASK¶
Address: 0xf0003800 + 0x14 = 0xf0003814
DRAM address mask for DMA transfers
READER_DATA_MASK¶
Address: 0xf0003800 + 0x18 = 0xf0003818
Pattern memory address mask
READER_DATA_DIV¶
Address: 0xf0003800 + 0x1c = 0xf000381c
Pattern memory address divisior-1
READER_INVERTER_DIVISOR_MASK¶
Address: 0xf0003800 + 0x20 = 0xf0003820
Divisor mask for selecting rows for which pattern data gets inverted
READER_INVERTER_SELECTION_MASK¶
Address: 0xf0003800 + 0x24 = 0xf0003824
Selection mask for selecting rows for which pattern data gets inverted
READER_ERROR_COUNT¶
Address: 0xf0003800 + 0x28 = 0xf0003828
Number of errors detected
READER_SKIP_FIFO¶
Address: 0xf0003800 + 0x2c = 0xf000382c
Skip waiting for user to read the errors FIFO
READER_ERROR_OFFSET¶
Address: 0xf0003800 + 0x30 = 0xf0003830
Current offset of the error
READER_ERROR_DATA3¶
Address: 0xf0003800 + 0x34 = 0xf0003834
Bits 96-127 of READER_ERROR_DATA. Erroneous value read from DRAM memory
READER_ERROR_DATA2¶
Address: 0xf0003800 + 0x38 = 0xf0003838
Bits 64-95 of READER_ERROR_DATA.
READER_ERROR_DATA1¶
Address: 0xf0003800 + 0x3c = 0xf000383c
Bits 32-63 of READER_ERROR_DATA.
READER_ERROR_DATA0¶
Address: 0xf0003800 + 0x40 = 0xf0003840
Bits 0-31 of READER_ERROR_DATA.
READER_ERROR_EXPECTED3¶
Address: 0xf0003800 + 0x44 = 0xf0003844
Bits 96-127 of READER_ERROR_EXPECTED. Value expected to be read from DRAM memory
READER_ERROR_EXPECTED2¶
Address: 0xf0003800 + 0x48 = 0xf0003848
Bits 64-95 of READER_ERROR_EXPECTED.
READER_ERROR_EXPECTED1¶
Address: 0xf0003800 + 0x4c = 0xf000384c
Bits 32-63 of READER_ERROR_EXPECTED.
READER_ERROR_EXPECTED0¶
Address: 0xf0003800 + 0x50 = 0xf0003850
Bits 0-31 of READER_ERROR_EXPECTED.
READER_ERROR_READY¶
Address: 0xf0003800 + 0x54 = 0xf0003854
Error detected and ready to read
READER_ERROR_CONTINUE¶
Address: 0xf0003800 + 0x58 = 0xf0003858
Continue reading until the next error