SDRAM¶
Register Listing for SDRAM¶
Register |
Address |
---|---|
SDRAM_DFII_CONTROL¶
Address: 0xf0006000 + 0x0 = 0xf0006000
Control DFI signals common to all phases
Field |
Name |
Description |
||||||
---|---|---|---|---|---|---|---|---|
[0] |
SEL |
|
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[1] |
CKE |
DFI clock enable bus |
||||||
[2] |
ODT |
DFI on-die termination bus |
||||||
[3] |
RESET_N |
DFI clock reset bus |
SDRAM_DFII_PI0_COMMAND¶
Address: 0xf0006000 + 0x4 = 0xf0006004
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI0_COMMAND_ISSUE¶
Address: 0xf0006000 + 0x8 = 0xf0006008
SDRAM_DFII_PI0_ADDRESS¶
Address: 0xf0006000 + 0xc = 0xf000600c
DFI address bus
SDRAM_DFII_PI0_BADDRESS¶
Address: 0xf0006000 + 0x10 = 0xf0006010
DFI bank address bus
SDRAM_DFII_PI0_WRDATA¶
Address: 0xf0006000 + 0x14 = 0xf0006014
DFI write data bus
SDRAM_DFII_PI0_RDDATA¶
Address: 0xf0006000 + 0x18 = 0xf0006018
DFI read data bus
SDRAM_DFII_PI1_COMMAND¶
Address: 0xf0006000 + 0x1c = 0xf000601c
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI1_COMMAND_ISSUE¶
Address: 0xf0006000 + 0x20 = 0xf0006020
SDRAM_DFII_PI1_ADDRESS¶
Address: 0xf0006000 + 0x24 = 0xf0006024
DFI address bus
SDRAM_DFII_PI1_BADDRESS¶
Address: 0xf0006000 + 0x28 = 0xf0006028
DFI bank address bus
SDRAM_DFII_PI1_WRDATA¶
Address: 0xf0006000 + 0x2c = 0xf000602c
DFI write data bus
SDRAM_DFII_PI1_RDDATA¶
Address: 0xf0006000 + 0x30 = 0xf0006030
DFI read data bus
SDRAM_DFII_PI2_COMMAND¶
Address: 0xf0006000 + 0x34 = 0xf0006034
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI2_COMMAND_ISSUE¶
Address: 0xf0006000 + 0x38 = 0xf0006038
SDRAM_DFII_PI2_ADDRESS¶
Address: 0xf0006000 + 0x3c = 0xf000603c
DFI address bus
SDRAM_DFII_PI2_BADDRESS¶
Address: 0xf0006000 + 0x40 = 0xf0006040
DFI bank address bus
SDRAM_DFII_PI2_WRDATA¶
Address: 0xf0006000 + 0x44 = 0xf0006044
DFI write data bus
SDRAM_DFII_PI2_RDDATA¶
Address: 0xf0006000 + 0x48 = 0xf0006048
DFI read data bus
SDRAM_DFII_PI3_COMMAND¶
Address: 0xf0006000 + 0x4c = 0xf000604c
Control DFI signals on a single phase
Field |
Name |
Description |
---|---|---|
[0] |
CS |
DFI chip select bus |
[1] |
WE |
DFI write enable bus |
[2] |
CAS |
DFI column address strobe bus |
[3] |
RAS |
DFI row address strobe bus |
[4] |
WREN |
DFI write data enable bus |
[5] |
RDEN |
DFI read data enable bus |
SDRAM_DFII_PI3_COMMAND_ISSUE¶
Address: 0xf0006000 + 0x50 = 0xf0006050
SDRAM_DFII_PI3_ADDRESS¶
Address: 0xf0006000 + 0x54 = 0xf0006054
DFI address bus
SDRAM_DFII_PI3_BADDRESS¶
Address: 0xf0006000 + 0x58 = 0xf0006058
DFI bank address bus
SDRAM_DFII_PI3_WRDATA¶
Address: 0xf0006000 + 0x5c = 0xf000605c
DFI write data bus
SDRAM_DFII_PI3_RDDATA¶
Address: 0xf0006000 + 0x60 = 0xf0006060
DFI read data bus
SDRAM_CONTROLLER_TRP¶
Address: 0xf0006000 + 0x64 = 0xf0006064
SDRAM_CONTROLLER_TRCD¶
Address: 0xf0006000 + 0x68 = 0xf0006068
SDRAM_CONTROLLER_TWR¶
Address: 0xf0006000 + 0x6c = 0xf000606c
SDRAM_CONTROLLER_TWTR¶
Address: 0xf0006000 + 0x70 = 0xf0006070
SDRAM_CONTROLLER_TREFI¶
Address: 0xf0006000 + 0x74 = 0xf0006074
SDRAM_CONTROLLER_TRFC¶
Address: 0xf0006000 + 0x78 = 0xf0006078
SDRAM_CONTROLLER_TFAW¶
Address: 0xf0006000 + 0x7c = 0xf000607c
SDRAM_CONTROLLER_TCCD¶
Address: 0xf0006000 + 0x80 = 0xf0006080
SDRAM_CONTROLLER_TCCD_WR¶
Address: 0xf0006000 + 0x84 = 0xf0006084
SDRAM_CONTROLLER_TRTP¶
Address: 0xf0006000 + 0x88 = 0xf0006088
SDRAM_CONTROLLER_TRRD¶
Address: 0xf0006000 + 0x8c = 0xf000608c
SDRAM_CONTROLLER_TRC¶
Address: 0xf0006000 + 0x90 = 0xf0006090
SDRAM_CONTROLLER_TRAS¶
Address: 0xf0006000 + 0x94 = 0xf0006094
SDRAM_CONTROLLER_TZQCS¶
Address: 0xf0006000 + 0x98 = 0xf0006098
SDRAM_CONTROLLER_LAST_ADDR_0¶
Address: 0xf0006000 + 0x9c = 0xf000609c
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_0¶
Address: 0xf0006000 + 0xa0 = 0xf00060a0
SDRAM_CONTROLLER_LAST_ADDR_1¶
Address: 0xf0006000 + 0xa4 = 0xf00060a4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_1¶
Address: 0xf0006000 + 0xa8 = 0xf00060a8
SDRAM_CONTROLLER_LAST_ADDR_2¶
Address: 0xf0006000 + 0xac = 0xf00060ac
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_2¶
Address: 0xf0006000 + 0xb0 = 0xf00060b0
SDRAM_CONTROLLER_LAST_ADDR_3¶
Address: 0xf0006000 + 0xb4 = 0xf00060b4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_3¶
Address: 0xf0006000 + 0xb8 = 0xf00060b8
SDRAM_CONTROLLER_LAST_ADDR_4¶
Address: 0xf0006000 + 0xbc = 0xf00060bc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_4¶
Address: 0xf0006000 + 0xc0 = 0xf00060c0
SDRAM_CONTROLLER_LAST_ADDR_5¶
Address: 0xf0006000 + 0xc4 = 0xf00060c4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_5¶
Address: 0xf0006000 + 0xc8 = 0xf00060c8
SDRAM_CONTROLLER_LAST_ADDR_6¶
Address: 0xf0006000 + 0xcc = 0xf00060cc
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_6¶
Address: 0xf0006000 + 0xd0 = 0xf00060d0
SDRAM_CONTROLLER_LAST_ADDR_7¶
Address: 0xf0006000 + 0xd4 = 0xf00060d4
SDRAM_CONTROLLER_LAST_ACTIVE_ROW_7¶
Address: 0xf0006000 + 0xd8 = 0xf00060d8